Before proceeding to analysis of microcontroller architecture the followng definitions will be given:
Microprocessor - a circuit that can perform any function depending on the program that it has to execute.
Program - a set of instructions executed one after another.
Instruction - an action that can be executable by the microcontroller core.
Core - main part of microcontroller that executes instructions in the program.
Microcontroller - a minicomputer that includes the following components: microprocessor core, program memory and peripheral modules. In general the MCU (microcontroller) takes the information from input interfaces, processes it and applies the result to the output interface.
Microcontroller Core Architecture
The AVR microcontroller has an 8-bit RISC architecture built on the Haward architecture principle. Such architecture allows most instructions to be executed in a single clock of the clock signal. Therefore, at a frequency of 1 MHz clock signal, can be executed up to one million operations per second - 1MIPS / MHz. Schematic AVR architecture can be represented by the figure below:
- PM - Programming memory. Here are stored the instructions that have to be executed by the MCU.
- PC - Program counter based on a register counter that selects the instructions from program memory. Normally, the PC itself performs the automatic modification through increments ensuring the successive implementation of instructions from the PM. However, it may load a value of CDC, which will perform jumps to conditional and unconditional jump instructions.
- CDC - command decoder. The CDC configures the core to execute the selected instruction taking into account the flag values of SREG status register.
- ALU - arithmetic logic unit. It executes arithmetical and logical instructions. The data to ALU is supplied by general purpose registers, each operand being selected by the CDC according to the current instruction, as well as data storage.
- GPR - general purpose registers, working registers of the MCU. Data processing for the AVR architecture is restricted to the use of at least one general purpose register, ie any transfer instruction or data processing occurs involving a general-purpose register.
- RAM - random access memory, working memory for big data.
- SREG - state register of MCU. Any data processing operation involving their processing by ALU, reports to the SREG register with changing its flags, presenting additional data about the operation result. It is placed in the address space of peripheral registers. The content of this register is accessible for writing and reading.
• Z - Zero. It will be set to 1 in case the result will be equal to 0.
• N - Negative. It will be set to 1 in case the 7th bit of the result will be 1.
• V - carry in signed operations.
• S - sign. It will be set to 1 if the result will be smaller than 0.
• H - mid-carry. It will be set to 1 in case of occurence of carry at 4th bit (in the middle of the outcome/result).
• T - temporarily bit. Used for storing 1 bit information of a general purpose register. It can be written / read by BST / BLD.
• I - interrupt permission bit. If it is set to 0 the interrupts are disabled, if 1 - allowed. It can be set or reset by CLI / SEI commands or when the interrupt processing subroutine is automatically called/returned by RETI.
• I / O Reg - access registers of peripheral modules such as GPIO, Ext INT, TIMER, etc.
The instruction execution inside the microcontroller core
The instruction itself is selected from PM (program memory) by using the PC (program counter) and is sent to the command decoder (CDC). The CDC decodes the command and generates the core configuration signals.
If the instruction is a processing, arithmetical or logical one to ALU will be generated a function selection signal and addresses for the left LA and right RA operand. The address for storing the result coincides with the address of the left operand LA. Once the result evaluation is performed will be generated the processor status bits that are stored in the SREG status register.
In case the instruction is a conditional jump instruction, if is satisfied the assumed condition of instruction by checking the state bits in SREG, will be generated a jump address to be registered in the program counter (PC). Similarly is generated the jump address for unconditional jump instructions, the only difference is that here are taken into consideration the SREG status bits.
For carry operations are generated the addresses to memory modules from which the carry is performed. It is important here to emphasize that for the AVR architecture are possible carry operations in which is strictly involved a general-purpose register (GPR).
Memory organization in AVR architecture
In the AVR architecture are present the following memory types:
• PM - Programming Memory
• GPR - General Purpose Registers
• I / O - Peripheral Access Registers
• RAM - Random Access Memory
• EEPROM - Permanent Memory
Memory blocks are grouped into three address spaces: program memory, data memory and EEPROM, representing three segments: code segment, data segment and EEPROM segment.
Unlike the program segment and the EEPROM segment, the data segment is made up of three memory types (as can be seen from the above figure). Therefore, general purpose registers, peripheral registers and RAM memory are placed in the same address space.
The operand registers in the most arithmetical logical and carry operations are placed starting with general purpose address 0x000, are found in t0 and occupy 32 locations.
The peripheral registers are placed immediately after the general purpose registers, starting with the address 32 (0x0020) and are used for access to the microcontroller peripheries.
Immediately after I/O registers is situated the address space for RAM memory that can be divided into two parts: Internal memory that is a component of the microcontroller chip and External memory that can be attached to it through certain pins.